AMD Extends Market-Leading FPGA Portfolio with AMD Spartan UltraScale Family Built for Cost-Sensitive Edge Applications

— New FPGAs offer high I/O counts, power efficiency, and state-of-the-art security features for embedded vision, healthcare, industrial networking, robotics, and video applications —

SANTA CLARA, Calif., March 05, 2024 (GLOBE NEWSWIRE) -- AMD (NASDAQ: AMD) today announced the AMD Spartan™ UltraScale+™ FPGA family, the newest addition to the extensive portfolio of AMD Cost-Optimized FPGAs and adaptive SoCs. Delivering cost and power-efficient performance for a wide range of I/O-intensive applications at the edge, Spartan UltraScale+ devices offer the industry’s highest I/O to logic cell ratio in FPGAs built in 28nm and lower process technologyⁱ, deliver up to 30 percent lower total power consumption versus the previous generationⁱⁱ, and contain the most robust set of security featuresⁱⁱⁱ in the AMD Cost-Optimized Portfolio.

“For over 25 years the Spartan FPGA family has helped power some of humanity’s finest achievements, from lifesaving automated defibrillators to the CERN particle accelerator advancing the boundaries of human knowledge,” said Kirk Saban, corporate vice president, Adaptive and Embedded Computing Group, AMD. “Building on proven 16nm technology, the Spartan UltraScale+ family’s enhanced security and features, common design tools, and long product lifecycles further strengthen our market-leading FPGA portfolio and underscore our commitment to delivering cost-optimized products for customers.”

Flexible I/O Interfacing and Power Efficient Compute
Spartan UltraScale+ FPGAs are optimized for the edge, delivering high I/O counts and flexible interfaces which allow the FPGAs to seamlessly integrate and efficiently interface with multiple devices or systems to address the explosion of sensors and connected devices.

The family offers the industry’s highest I/O to logic cell ratio of FPGAs built on 28nm and below process technology, with up to 572 I/Os and voltage support up to 3.3V, enabling any-to-any connectivity for edge sensing and control applications. The proven 16nm fabric and support for a wide array of packaging, starting as small as 10x10mm, provide high I/O density in an ultra-compact footprint. The extensive AMD FPGA portfolio also provides the scalability to start with cost-optimized FPGAs and continue through to midrange and high-end products.

The Spartan UltraScale+ family is estimated to offer up to a 30 percent reduction in power compared to the 28nm Artix™ 7 family, through 16nm FinFET technology and hardened connectivity. They are the first AMD UltraScale+ FPGAs with a hardened LPDDR5 memory controller and PCIe^® Gen4 x8 support, providing both power efficiency and future-ready capabilities for customers.

State-of-the-Art Security Features
Spartan UltraScale+ FPGAs offer the most state-of-the-art security features in the AMD Cost-Optimized FPGA portfolio.

• Protecting IP: Support for Post-Quantum Cryptography with NIST-approved algorithms offers state-of-the-art IP protection against evolving cyber-attacks and threats. A physical unclonable function provides each device with a unique fingerprint for added security.
• Preventing tampering: PPK/SPK key support helps manage obsolete or compromised security keys while differential power analysis helps protect against side-channel attacks. The devices contain a permanent tamper penalty to further protect against misuse.
• Maximizing uptime: Enhanced single-event upset performance helps fast and secure configuration with increased reliability for customers.
  

The entire AMD portfolio of FPGAs and adaptive SoCs are supported by the AMD Vivado™ Design Suite and Vitis™ Unified Software Platform, allowing hardware and software designers to leverage the productivity benefits of these tools and included IPs via a single designer cockpit from design to verification.

AMD Spartan UltraScale+ FPGA family sampling and evaluation kits are expected to be available in the first half of 2025. Documentation is available today with tools support starting with the AMD Vivado Design Suite in the fourth quarter of 2024.   

Supporting Resources

• Learn more about Spartan UltraScale+ FPGAs
• Follow AMD on LinkedIn
• Follow AMD on Twitter
  

About AMD
For more than 50 years AMD has driven innovation in high-performance computing, graphics, and visualization technologies. Billions of people, leading Fortune 500 businesses, and cutting-edge scientific research institutions around the world rely on AMD technology daily to improve how they live, work, and play. AMD employees are focused on building leadership high-performance and adaptive products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit the AMD (NASDAQ: AMD) website, blog, LinkedIn, and Twitter pages.

©2024 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, Artix, Spartan, UltraScale+, Vitis, Vivado, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other names used herein are for informational purposes only and may be trademarks of their respective owners.

ⁱ Based on product datasheets for AMD Spartan™ UltraScale+™ FPGAs and published datasheets for Efinix, Intel, Lattice, and Microchip as of February 2024, comparing the total I/O to logic cell ratios of comparable 28nm and lower node size FPGAs. (SUS-11)

ⁱⁱ Projection is based on an AMD Labs internal analysis in January 2024, using total power calculation (static plus dynamic power) based on the difference in logic cell count of an AMD Artix™ UltraScale+ AU7P FPGA, to estimate the power of a 16nm AMD Spartan™ UltraScale+™ SU35P FPGA, versus a 28nm AMD Artix 7 7A35T FPGA, using Xilinx Power Estimator (XPE) tool version 2023.1.2. Total power may vary when products are released in market and based on configuration, usage, and other factors. (SUS-03)

ⁱⁱⁱ Based on AMD internal analysis in December 2023, using the product datasheets to compare the number of security features in Spartan™ UltraScale+™ FPGAs to previous generation AMD cost-optimized FPGAs. (SUS-02)

^iv Revenue data, Omdia Competitive Landscape Tool CTL, Quarterly Semiconductor Market Share. November 2023.

Contact:
Mike Sanchez
 AMD Communications
+1 209 262-7458
M.Sanchez@amd.com

Suresh Bhaskaran
AMD Investor Relations
+1 408-749-2845
Suresh.Bhaskaran@amd.com

A photo accompanying this announcement is available at https://www.globenewswire.com/NewsRoom/AttachmentNg/7a0338aa-8711-4a93-b16b-f699f5f0eb3c